SDT028TFT connections

Yossi,

Per the Ilitek ILI9320 spec, page 44:

7.5.5. 16-bit RGB Interface
The 16-bit RGB interface is selected by setting the RIM[1:0] bits to ““01””. The display operation is synchronized with VSYNC, HSYNC, and DOTCLK signals. Display data are transferred to the internal RAM in synchronization with the display operation via 16-bit RGB data bus (DB17-13, DB11-1) according to the data enable signal (ENABLE). Registers are set only via the system interface.

Page 30& 31:
7.3.    Serial Peripheral Interface (SPI)
The Serial Peripheral Interface (SPI) is selected by setting the IM[3:0] pins as ““010x”” level. The chip select pin
(nCS), the serial transfer clock pin (SCL), the serial data input pin (SDI) and the serial data output pin (SDO) are used in SPI mode. The ID pin sets the least significant bit of the identification code. The DB[17:0] pins, which are not used, must be tied to either IOVcc or DGND.
The SPI interface operation enables from the falling edge of nCS and ends of data transfer on the rising edge of nCS. The start byte is transferred to start the SPI interface and the read/write operation and RS information are also included in the start byte. When the start byte is matched, the subsequent data is received by ILI9320.
The seventh bit of start byte is RS bit. When RS = ““0””, either index write operation or status read operation is executed. When RS = ““1””, either register write operation or RAM read/write operation is executed. The eighth bit of the start byte is used to select either read or write operation (R/W bit). Data is written when the R/W bit is ““0”” and read back when the R/W bit is ““1””.
After receiving the start byte, ILI9320 starts to transfer or receive the data in unit of byte and the data transfer starts from the MSB bit. All the registers of the ILI9320 are 16-bit format and receive the first and the second byte datat as the upper and the lower eight bits of the 16-bit register respectively. In SPI mode, 5 bytes dummy read is necessary and the valid data starts from 6th byte of read back data.

Vcc and IoVCC: It must be between 2.7~2.9V, it may be possible with the controller however the TFT glass panel has it's own spec and that is why we say between 2.7~2.9V.

I've read pages 30 and 31 and this is exactly why I've asked the question about the SPI.
I need to use 18-bit RGB mode and in order to setup the registers, I'll need to use SPI so how come the instructions says: "The DB[17:0] pins, which are not used, must be tied to either IOVcc or DGND"?

Regarding the VCC & VCCIO, If the TFT panel has its own spec, I can understand why VCC is not 3.3V, but how come VCCIO, which drive the controller's I/O can't be 3.3V.
This is not a simple thing to add a level translator for more than 24 pins in a very tight space application so the 2.7-2.9V limit should be really considered carefully.

Thanks,
Yossi

Yossi,

Please contact your local sales representative regarding a replacement TFT, part number SDT028ATFT.

Regards,
Trevor