Serial Connectivity and Power Clarification
I'm working with S128240D series is 8-bit serial mode (design based on the sample schematic + code) and so far, the best observed is 2.7 Volts on the VLCD pin and blank LCD. Can we verify the following is the correct 4-wire serial set up?
- The sample Schematic is calling for 3V and seems to be running 7x Boost (current set up). I understand this may be too much and 6x or 5x are preferred.
- it is OK to run 3.2v +/- 50mV
- SPI clock settings: MSB_FIRST, SECOND_EDGE, FALLING_LEAD
- Reset held High during operation
- XCS low before and during byte transfer
- D7-D0, RW, ERD pulled to up to VDD
- A0 Low = Command byte, High = LCD Data byte
- IF1-3 tied to GND for 8-bite serial
The sample code also uses some busy loop delay routines (Delay1-3). What should be the time period (as opposed to MCU clock based time)?
Thanks,
Armand
Update:
Added a few (us) defensive delays before and aft byte transmission before changing XCS. Booster circuit can now be turned on and off via commands. While ON, VLCD reads 18V (6X) and V0in/out 14V per VolumeCTRL. Screen? still blank.
Shouldn't there be a command I can send that would at least flicker the display area? e.g. a "Hello, World!" equivalent.
-Armand
In case someone else comes across this tumble-weed in the future:
Provided that the reset delays are observed, the above settings + (6x boost, 3.2V) seem to work @ 6Mhz clock, even without wait/delays for XCS/A0 (ST7529 spec pg76 show min setup/hold times that are within of the 50ns phase delay of second edge 10Mhz clock.
-Armand
I'm working with S128240D series is 8-bit serial mode (design based on the sample schematic + code) and so far, the best observed is 2.7 Volts on the VLCD pin and blank LCD. Can we verify the following is the correct 4-wire serial set up?
- The sample Schematic is calling for 3V and seems to be running 7x Boost (current set up). I understand this may be too much and 6x or 5x are preferred.
Trevor: Yes, 6X is OK.- it is OK to run 3.2v +/- 50mV
Trevor: Yes- SPI clock settings: MSB_FIRST, SECOND_EDGE, FALLING_LEAD
Trevor: Please see the new attached sample code- Reset held High during operation
Trevor: Yes- XCS low before and during byte transfer
Trevor: Yes- D7-D0, RW, ERD pulled to up to VDD
Trevor: Yes- A0 Low = Command byte, High = LCD Data byte
Trevor: Please see the new attached sample code- IF1-3 tied to GND for 8-bite serial
Trevor: YesThe sample code also uses some busy loop delay routines (Delay1-3). What should be the time period (as opposed to MCU clock based time)?
Thanks,
Armand
-armandr
Attachment: AE45_S1.C (11.0KB)